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处理器指令流水线操作  

2007-06-09 22:42:53|  分类: Digital |  标签: |举报 |字号 订阅

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   Five stage pipeline architecture:

   IF instruction fetch, PC is address into memory fetching instruction
   ID instruction decode and register read out of two values
   EX execute instruction or compute data memory address
   M   data memory access to store or fetch a data word
   WB write back value into general register


          IF        ID           EX         M        WB
     +--+      +--+         +--+      +--+      +--+
     |   |      |   |         | A|-|\   |   |      |   |
     |   |      |   |     /---|   | \ \_|   |      |   |
     |PC|-(I)-|IR|-(R)   = |   | / / |   |-(D)-|   |--+
     |   |      |   |   ^ \---| B|-|/   |   |      |   |   |
     +--+      +--+   |      +--+      +--+      +--+   |
      ^         ^     |       ^    ALU   ^         ^     |
      |         |     |       |         |         |     |
clk-+--------+-----------+--------+--------+     |
                    |                              |
                    +-----------------------------+

   Now consider the instruction sequence:

   400   lw   $1,100($0)   load general register 1 from memory location 100
   404   lw   $2,104($0)   load general register 2 from memory location 104
   408   nop
   40C   nop              wait for register $2 to get data
   410   add $3,$1,$2     add contents of registers 1 and 2, sum into register 3
   414   nop
   418   nop              wait for register $3 to get data
   41C   add $4,$3,$1     add contents of registers 3 and 1, sum into register 4
   420   nop
   424   nop              wait for register $4 to get data
   428   beq $3,$4,-100   branch if contents of register 3 and 4 are equal to 314
   42C   add $4,$4,$4     add ..., this is the "delayed branch slot" always exec.


   The pipeline stage table with NO data forwarding is:

   lw    IF ID EX M   WB
   lw       IF ID EX M   WB
   nop         IF ID EX M   WB
   nop            IF ID EX M   WB
   add               IF ID EX M   WB
   nop                  IF ID EX M   WB
   nop                     IF ID EX M   WB
   add                        IF ID EX M   WB
   nop                           IF ID EX M    WB
   nop                              IF ID EX M   WB
   beq                                 IF ID EX M   WB
   add                                    IF ID EX M   WB

   time 1   2   3   4   5   6   7   8   9   10 11 12 13 14 15 16


This can be significantly improved with the addition of four
multiplexors and wiring.



          IF        ID                   EX           M        WB
     +--+      +--+            +--+           +--+        +--+
     |   |      |   |            | A|-(X)--|\   |   |        |   |
     |   |      |   |     /-(X)--|   | | |   \ \_|   |        |   |
     |PC|-(I)-|IR|-(R)    | = |   | | |   / / |   |-+-(D)-|   |--+
     |   |      |   |   ^ \-(X)--| B|-(X)--|/   |   | |      |   |   |
     +--+      +--+   |     |    +--+ | |       +--+ |      +--+   |
      ^         ^     |     |     ^    | |   ALU   ^    |       ^     |
      |         |     |     |     |    | |        |    |       |     |
clk-+--------+--------------+-------------+----------+     |
                    |     |         | |            |            |
                    |     +----------+-----------+            |
                    |              |                          |
                    +-------------+-------------------------+

   The pipeline stage table with data forwarding is:

   lw    IF ID EX M   WB
   lw       IF ID EX M   WB
   nop         IF ID EX M   WB                  saved one nop
   add            IF ID EX M   WB               $2 in WB and used in EX
   add               IF ID EX M   WB            saved two nop's $3 used
   nop                  IF ID EX M WB          saved one nop        
   beq                     IF ID EX M   WB      $4 in MEM and used in ID
   add                        IF ID EX M   WB

   time 1   2   3   4   5   6   7   8   9   10 11 12

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