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DLL的VERILOG实现 - (原)  

2007-06-19 01:05:32|  分类: Digital |  标签: |举报 |字号 订阅

  下载LOFTER 我的照片书  |

     很久以前做的一老代码, 主要项目忙得紧, 没来得及放进芯片里去, 这里拿出来分享给有兴趣的朋友, 希望对侬有所益处. 此代码实现并测试DTV行场扫描数字校正的延迟锁定环路.

//*****Project: DLL for HV scaning   *******
//*****Designer: Paul Zhang****************

`timescale 1ns/100ps

module   hvDLL_tb;
//The parameter
parameter DELAY = 0;
parameter DELAY_ONE_CELL = 0.1;  
parameter IMAGE_DEPTH = 720*480 ;    
parameter PERIOD_pclk = 10;                 
parameter PERIOD_miniclk = 0.1;            
parameter PERIOD_hclk = 7200;    
parameter H_WIDTH = 720;                     
parameter V_WIDTH = 480;               
parameter CNT_miniclk=PERIOD_hclk*PERIOD_miniclk;         

reg pclk,miniclk,rst_n;
reg hout_m,pdup,pddn,lockp1,lockp2;
reg [15:0]     memsin [V_WIDTH-1:0];
reg [6:0] inmem; reg [7:0] diffsum;

reg [63:0]   bub0,bub1,bub2,bub3,bub4;

wire hclk,hfly,hout,houtn,hclkn,hsf,hsb;//houtf,houtb,jtp;
wire pd_rst_n,pdup_d,pddn_d,pdup_n,pddn_n;
wire [9:0] skewvar;
wire [127:0] bubble,bubble_tmp;
wire [6:0]    sbub0,sbub1,sbub2,sbub3,sbub4,sdiff0,sdiff1,sdiff2,sdiff3;
wire [127:0] sel_dly;
reg [127:0] sel_dly_reg;
wire hclkd1,hclkd2,lockd;
integer ii;

//****** Generate clock & reset *****************
//The clock and negedge reset
initial begin pclk = 1'b1;
       forever #(PERIOD_pclk/2) pclk = ~pclk;end
initial begin miniclk = 1'b1;
       forever #(PERIOD_miniclk/2) miniclk = ~miniclk;end
initial begin rst_n = 1;#30 rst_n = 0; #75 rst_n = 1; end
//The h-counter and v-counter
reg [10:0] h_cnt ;                 // Horizontal counter.
always @(posedge pclk or negedge rst_n)
    if(!rst_n) h_cnt <= 11'b0;else begin
       if(h_cnt == H_WIDTH -1) h_cnt <= 11'b0;
       else h_cnt <= h_cnt + 1'b1;end
assign hclk=h_cnt<(H_WIDTH/2);

reg [9:0] v_cnt ;                 // Vertical counter.
always @(posedge hclk or negedge rst_n)
    if(!rst_n) v_cnt <= 10'b0;else begin
       if(v_cnt == (V_WIDTH -1)) v_cnt <= 10'b0;
       else v_cnt <= v_cnt + 1'b1;end
//---- generate hfly w/skew based on hout ------
reg [19:0] mini_cnt;                 // dummy counter.
reg [19:0] mini_cnt_max;
reg hout_d,hclk_d,hout_dd,hclk_dd;
wire hclk_r,hout_r,hclk_rr,hout_rr;
wire houts;
always @(posedge miniclk or negedge rst_n)
    if(!rst_n) begin mini_cnt<=20'd0;mini_cnt_max<=20'd0;end
    else if(hout_r) begin mini_cnt_max<=mini_cnt;mini_cnt<=mini_cnt+1'b1;end
    else if(hout_rr|hclk_rr) mini_cnt <= 20'd0;
    else mini_cnt <= mini_cnt + 1'b1;
always @(posedge miniclk or negedge rst_n)
    if(!rst_n) begin hout_d<=1'b0;hout_dd<=1'b0;hclk_d<=1'b0;hclk_dd<=1'b0;end
    else begin hout_d<=hout;hout_dd<=hout_d;hclk_d<=hclk;hclk_dd<=hclk_d;end
assign hout_r=(~hout)&hout_d;
assign hclk_r=(~hclk)&hclk_d;
assign hout_rr=(~hout_d)&hout_dd;
assign hclk_rr=(~hclk_d)&hclk_dd;
assign houts=inmem[6]?((mini_cnt>mini_cnt_max-inmem[5:0])|(mini_cnt<CNT_miniclk/4)):
          ((mini_cnt>inmem[5:0])&(mini_cnt<CNT_miniclk/4));

initial begin $readmemb("s1.txt",memsin);end
always @(posedge hclk or negedge rst_n)
    if(!rst_n) inmem <= 16'd0;
    else inmem   <= memsin[v_cnt];
assign hfly = houts;
//******* DLL loop *************
assign hsb = h_cnt>(H_WIDTH/2-1); //--before one pixel
assign hsf = h_cnt>(H_WIDTH/2);

always @(posedge pclk or negedge rst_n or negedge pdup_n)
    if(!rst_n) sel_dly_reg <= 128'd0;else
    begin
       if((h_cnt == 11'd1)|(sel_dly_reg[126] )) sel_dly_reg <= 128'd1;
       else if(lockd) sel_dly_reg<=sel_dly_reg;
       else if(jtp) sel_dly_reg <= sel_dly_reg>>1;
       else sel_dly_reg <= 1'd1 + sel_dly_reg<<1;
    end

assign sel_dly=sel_dly_reg;
dll_delay_line dll_delay_line_up ( .in1(hsf), .out1(hout), .sel(sel_dly));

always @(posedge hfly or negedge rst_n)
    if(!rst_n) lockp1 <= 1'b0;
    else lockp1 <= hclk;
INVX2 INV_dd1 (.A(hclk),.Y(hclkd1));
INVX2 INV_dd2 (.A(hclkd1),.Y(hclkd2));
always @(posedge hfly or negedge rst_n)
    if(!rst_n) lockp2 <= 1'b0;
    else lockp2 <= hclkd2;
assign lockd=(~((~lockp1)&(~lockp2)))&(~lockp2);

//DFFNRX1 DFF1_d1(.Q(pdup), .QN(), .D(1'b1), .CKN(hclk), .RN(pd_rst_n));
//DFFNRX1 DFF1_d2(.Q(pddn), .QN(), .D(1'b1), .CKN(hclk), .RN(pd_rst_n));
assign hclkn=~hclk;
always @(posedge hfly or negedge rst_n or negedge pd_rst_n)
    if(!rst_n | !pd_rst_n) pdup <= #DELAY 1'b0;
    else pdup <= 1'b1;
always @(posedge hclkn or negedge rst_n or negedge pd_rst_n)
    if(!rst_n | !pd_rst_n) pddn <= #DELAY 1'b0;
    else pddn <= 1'b1;

NAND2X1 NAND_d1(.Y(pd_rst_n),.A(pdup),.B(pddn));
INVX2 INV_d1 (.A(pddn),.Y(pddn_n));
INVX2 INV_d2 (.A(pddn_n),.Y(pddn_d));
INVX2 INV_d3 (.A(pdup),.Y(pdup_n));
INVX2 INV_d4 (.A(pdup_n),.Y(pdup_d));
//-------- delay line module ----
dll_delay_line_pass dll_delay_line_tdc (     
.in1(pdup_d),    
.out1(),    
.passout(bubble),
.sel(128'h3FFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF)
);

assign bubble_tmp=pdup_d?bubble:128'd0;
always @(posedge pdup_n or negedge rst_n)
    if(!rst_n) bub0 <= 64'd0;else
    begin
      bub1<=bub0;bub2<=bub1;bub3<=bub2;bub4<=bub3;
      for (ii=0;ii<64;ii=ii+1)   bub0[ii]<=bubble[ii*2+1];
    end

assign sbub0=bsum(bub0);
assign sbub1=bsum(bub1);
assign sbub2=bsum(bub2);
assign sbub3=bsum(bub3);
assign sbub4=bsum(bub4);
assign sdiff0=sbub1>sbub0?(sbub1-sbub0):{~(sbub0-sbub1)+1'b1};
assign sdiff1=sbub2>sbub1?(sbub2-sbub1):{~(sbub1-sbub2)+1'b1};
assign sdiff2=sbub3>sbub2?(sbub3-sbub2):{~(sbub2-sbub3)+1'b1};
assign sdiff3=sbub4>sbub3?(sbub4-sbub3):{~(sbub3-sbub4)+1'b1};

always @(posedge pdup_n or negedge rst_n)
    if(!rst_n) diffsum <= 8'd0;
    else diffsum <= (sdiff0+sdiff1+sdiff2+sdiff3)>>2;
assign jtp=diffsum[7];

//------- function --------------------------------------------------
function [63:0] bsum;
   input [63:0] A; integer ii;
begin for (ii=0;ii<64;ii=ii+1)
       if(A[ii]^A[ii+1]==1'b1) bsum=ii;end
endfunction

//------------- behavioul delay line for emulate jitter ----
endmodule

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