注册 登录  
 加关注
查看详情
   显示下一条  |  关闭
温馨提示!由于新浪微博认证机制调整,您的新浪微博帐号绑定已过期,请重新绑定!立即重新绑定新浪微博》  |  关闭

paul.mcdean的博客

 
 
 

日志

 
 

High Performance Synthesis -(6)  

2007-05-06 18:55:37|  分类: Digital |  标签: |举报 |字号 订阅

  下载LOFTER 我的照片书  |

Characterizing sub-blocks

When following the characterize/compile strategy, the sub-blocks should be compiled in series.  For example block A is characterized and recompiled, then block B is characterized and recompiled, etc.  The following example characterizes two sub-blocks (designA and designB) and re-compiles each.  The tighten_constraints.scr script is used to tighten the I/O constraints of the sub-block before the compile.

Example sub-block characterize/compile flow

characterize -constraints -connections {instA}

current_design designA

include tighten_constraints.scr -quiet

compile -inc -boundary_opt -map_effort high

current_design TOP_DESIGN

report_timing -net -trans -sig 3

characterize -constraints -connections {instB}

current_design designB

include tighten_constraints.scr -quiet

compile -inc -boundary_opt -map_effort high

current_design TOP_DESIGN

report_timing -net -trans -sig 3

After characterizing and compiling a block, return to the top-level and perform timing analysis.  Sometimes the top-level timing analysis will look worse then before the characterize/compile.  If this occurs perform a top level medium or high effort incremental compile.  Only then will the success of the characterize/compile be seen.

Characterizing DesignWare parts

All of the comments of Section 5.3.2.1 apply for DesignWare parts, with the addition of one step.  The part could be recompiled just like any other sub-block, however the potential for Incremental Implementation Selection (IIS) would be lost.  Design Compiler re-evaluates the implementation (e.g. RPL vs. CLA) of DesignWare parts during a compile or incremental compile.  By maintaining the DesignWare part as an instance within a parent block, Design Compiler makes it a candidate for IIS.  Placing the DesignWare part in a dummy level of hierarchy does this.

The following example recompiles a DesignWare part, instance u100, which resides in block TOP_DESIGN/blockA.  The instance name for blockA is blockA_0.  u100 is placed in a dummy level of hierarchy, this dummy level is then characterized, the I/O constraints are tightened and a high effort compile is done.  Note that a full compile (not an incremental) is performed.  This allows Design Compiler to restructure the DesignWare part from scratch, using the accurate timing constraints provided by characterize.

Example DesignWare characterize/compile flow

current_design blockA

group u100 -design dw_dummy -cell dw_dummy0

current_design TOP_DESIGN

characterize -constraints -connections {blockA_0/dw_dummy0}

current_design dw_dummy

include tighten_constraints.scr -quiet

compile -boundary_opt -map_effort high

current_design TOP_DESIGN

report_timing -net -trans -sig 3

Ungroup hierarchy

Design Compiler looks for opportunities for merging discrete cells into complex ones.  When a path crosses a hierarchical boundary, Design Compiler can not merge cells on opposite sides of the boundary.  This can result in more levels of logic and a longer delay on the path.

Examine the critical path for hierarchical crossings.  If it passes through numerous small blocks, ungroup these blocks and do a high effort incremental compile.  Also ungroup any DesignWare parts which lie on the critical path.  Any path within the critical range can benefit from this technique.  Many floorplan and layout tools automatically ungroup all hierarchy smaller than a certain size.  This hierarchy is a prime candidate for ungrouping.

Ungrouping hierarchy can improve the critical paths, but it can make them worse just as easily.  Paths can get worse when the sub-block that was ungrouped used a smaller wire-load model than its parent block.  This increases the load on each of the nets that were fully contained within the sub-block.  The designer must determine which wire-load model is most accurate.  If the sub-block is going to be ungrouped at the back-end anyway, the smaller wire-load model may be too optimistic.  For example, if the entire design is to be ungrouped in layout, the best results might be obtained by ungrouping all hierarchy within Design Compiler.  However this is tricky and several iterations of custom wire-load model creation may be required to find a wire-load model that accurately reflects the routing.

Improving high fanout nodes

The -nets switch on report_timing displays the fanout of each cell along the path.  If nets are found which have a high fanout, the net may benefit from a buffer tree.  Design Compiler can automatically add a structurally balanced tree of buffers via the balance_buffer command.  Note that this tree is not guaranteed to be delay balanced; there may be skew between each branch.  Therefore balance_buffer is not suited for clock tree synthesis.

To buffer the net n2 invoke ‘balance_buffer -net n2’.  The balance_buffer command has the limitation of only working within the current design.   If the high fanout net crosses hierarchy the designer may have to run balance_buffer several times or ungroup some of the hierarchy.

If many high fanout nets exist, an automated method is useful.  Solvit article SYNTH-480902 contains a combination Perl/dc_shell script that will run balance_buffer on all nets with fanout greater then a specified value.

While adding a buffer tree can reduce the delay of a high fanout net, a simpler technique is to manually size the driver cell.  This is done via the change_link command.  However before a cell is manually upsized, the designer should investigate why Design Compiler did not upsize the cell.  The reason is often an implicit dont_touch as discussed in Section 5.6.

  评论这张
 
阅读(37)| 评论(0)
推荐 转载

历史上的今天

评论

<#--最新日志,群博日志--> <#--推荐日志--> <#--引用记录--> <#--博主推荐--> <#--随机阅读--> <#--首页推荐--> <#--历史上的今天--> <#--被推荐日志--> <#--上一篇,下一篇--> <#-- 热度 --> <#-- 网易新闻广告 --> <#--右边模块结构--> <#--评论模块结构--> <#--引用模块结构--> <#--博主发起的投票-->
 
 
 
 
 
 
 
 
 
 
 
 
 
 

页脚

网易公司版权所有 ©1997-2018