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High Performance Synthesis -(3)  

2007-05-06 18:47:37|  分类: Digital |  标签: |举报 |字号 订阅

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Impact of set_max_area on timing

Starting in 1998.02 Design Compiler will perform minimal area optimization unless an area constraint is set.  Previous versions of Design Compiler always optimized for area if timing constraints were not met.  During area optimization Design Compiler maintains delay as a higher priority then area.  Area optimization sometimes uncovers opportunities for Design Compiler to make further timing improvements.  

Try compiling with and without a set_max_area constraint.  If the timing does not improve with it then consider forgoing the area constraint until later in the design cycle.  Early in the design cycle the priority is delay and getting results quickly; an area constraint will increase the run-time.  If a realistic area constraint is given, Design Compiler will quit the area optimization phase when it is reached.  A constraint of zero can be used, but Design Compiler will work longer before finally giving up.

Using boundary optimization

There are four types of optimizations which are collectively referred to as boundary optimization:

1)    Propagation of constants across hierarchy

2)    Propagation of Equal/Opposite information across hierarchy

3)    Propagation of unconnected port information across hierarchy

4)    Pushing inversions across hierarchy

This type of data is always propagated within a block but normally does not cross into sub-blocks.  When boundary optimization is enabled, all four types occur up and down the hierarchy.  This can result in a faster critical path and smaller design.  Enabling boundary optimization does not allow Design Compiler to share logic across the hierarchy; this can only happen if the hierarchy is ungrouped.

By defaul, the compile command will propagate constants and equal/opposite information up (not down) the hierarchy.  If the compile_preserve_subdesign_interfaces variable is set to TRUE even this basic level of propagation does not occur.  However if boundary optimization is enabled, the compile_preserve_subdesign_interfaces variable is ignored.

Characterize can activate a limited form of boundary optimization.  If ‘characterize
-connections
’ is used, the attributes for the first three forms of boundary optimization are applied to the inputs of the sub-block.  These attributes are propagated into the sub-block during any subsequent compile of that block, but will stop at any hierarchy below it.

Boundary optimization is enabled via the -boundary_optimization switch to the compile command.  Alternatively the set_boundary_optimization attribute can be set to true or false on individual designs, to invoke it during compile.

   Issues with boundary optimization

Although boundary optimization can improve compile results, there are several issues with using it that must be understood. A specific type of transform possible with boundary optimization is the elimination of inverter pairs separated by hierarchy.  This type of transform reduces delay on the path but changes the phase of the I/O port.  To represent this, Design Compiler adds ‘_BAR’ to the port name.  If gate-level simulation of the sub-block is performed the _BAR suffix may necessitate tweaks to the testbench.

This inverter pushing optimization also effects formal verification (FV).  Equivalence checking FV tools compare two versions of the same design for functional equivalence.  When performing a gates-to-gates check, the FV tool will try to match all I/O ports across the two designs.  Boundary optimization can change the phase and name of sub-block ports.  This creates a mismatch for the FV tool.  This is not an issue if FV can be done from the top-level (the top-level functionality is unchanged by boundary optimization).  If run-time dictates that FV be performed at the sub-block level, one strategy is to use the set_boundary_optimization command to activate boundary optimization only on the sub-blocks below the blocks that are compared with FV.   If this command is used to select specific blocks, remove the        
-boundary_optimization switch from the compile command.  A simpler work-around is to set compile_disable_hierarchical_inverter_opt = true.  This will disable the inverter pushing algorithm of boundary optimization.

Boundary optimization can change the functionality of a sub-block.  For example, consider two sub-block inputs that are ANDed together and fed to a flip-flop.  If both inputs are tied high at the parent block level, the AND gate is not needed and the flip-flop data input is tied high.  The top-level functionality has not been changed, however the function of the sub-block itself has changed.  By itself this is generally not an issue unless gate-level simulation is performed on the sub-block.  In that case, gate-level simulation results will differ from RTL simulation.  However, the top-level simulation results are the same.

Another issue involves recompiling of sub-blocks from RTL.  Constants within a sub-block will propagate out of the block and remove logic in the parent block.  Once again the top-level functionality is not affected, and the design becomes smaller and faster.  However, problems can occur if the sub-block RTL is modified, recompiled, and slipped into the existing parent design.  The constants that previously propagated out of the sub-block may have been removed by the RTL modifications.  Now the sub-block may be expecting certain logic within the parent block that has been removed by the previous boundary optimization compile.  The result is that the top-level functionality is changed.  If this flow is to be used, do not use boundary optimization, and set the compile_preserve_subdesign_interfaces variable to TRUE.

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