注册 登录  
 加关注
   显示下一条  |  关闭
温馨提示!由于新浪微博认证机制调整,您的新浪微博帐号绑定已过期,请重新绑定!立即重新绑定新浪微博》  |  关闭

paul.mcdean的博客

 
 
 

日志

 
 

High Performance Synthesis -(2)  

2007-05-06 18:45:37|  分类: Digital |  标签: |举报 |字号 订阅

  下载LOFTER 我的照片书  |

   Using a critical range

During a compile Design Compiler continuously works to improve the paths leading to the most critical endpoint (e.g. an output port or flip-flop).  The endpoint which is most critical will change from moment to moment as paths are improved.  Once Design Compiler determines it can not further improve the most critical endpoint it exits the delay optimization phase and moves into design rule fixing.

If a critical range is used, Design Compiler will work on more endpoints than just the most critical one.  Therefore if the most critical endpoint can not be further improved, Design Compiler will move on to the next most critical.  The critical range is set via the set_critical_range command (before 1998.02 this was compile_default_critical_range) whose argument is time (often in nano-seconds).  If a critical range of 2ns is specified, Design Compiler will work on optimizing the most critical endpoint and endpoints within 2ns of the most critical endpoint.  Note that critical range does not affect the initial mapping; the RTL is mapped to the target technology even if no critical range is set.  Also, even with a critical range Design Compiler will not work to improve paths that are already passing their timing constraint (to add margin, increase the -minus_uncertainty via the set_clock_skew command).

Using a critical range will often improve the worst violator in the design.  A very large critical range (e.g. 1000ns) will cause Design Compiler to work on all failing endpoints in the design.  This in turn will cause an undesirable increase in run-time.  The goal is to improve the worst violator with minimum increase in run-time.  Picking a small value for the critical range does this.  One rule of thumb is to use a value that is around one cell delay in your technology (e.g. 250ps).  If the design is already mapped to gates another rule of thumb is to run a ‘report_timing -path end -max_paths 20’ and pick a critical range that will force Design Compiler to work on all the endpoints shown.  The number 20 is a general guideline meant to keep run-time low.  

Another reason to use a critical range is to force Design Compiler to work on all failing endpoints before handing off to layout.  Even though the design may not meet the timing goal, the number of failing paths will be reduced (i.e. the Total Negative Slack is reduced).  This can be done by setting the critical range to any large number (say 1000ns). See Section 5.1 for further discussion of using critical range.

  评论这张
 
阅读(14)| 评论(0)
推荐 转载

历史上的今天

评论

<#--最新日志,群博日志--> <#--推荐日志--> <#--引用记录--> <#--博主推荐--> <#--随机阅读--> <#--首页推荐--> <#--历史上的今天--> <#--被推荐日志--> <#--上一篇,下一篇--> <#-- 热度 --> <#-- 网易新闻广告 --> <#--右边模块结构--> <#--评论模块结构--> <#--引用模块结构--> <#--博主发起的投票-->
 
 
 
 
 
 
 
 
 
 
 
 
 
 

页脚

网易公司版权所有 ©1997-2017